1. Technical Field
The present invention relates in general to address translation facilities in processors and in particular to logic circuits in processors for calculating effective addresses. Still more particularly, the present invention relates to effective address calculation in a processor which provides early determination of the next data fetch address.
2. Description of the Related Art
The address translation process is a necessary function in modern processors. Often the address translation circuits are directly in the critical path. For this reason, improvements in the delay or starting time of the translation circuits will usually be of substantial value. Address translation performance is also critical because load and store processor instructions, which require address translations, generally comprise a large percentage of the instructions encountered during execution of typical code by a processor.
The address translation process starts with an effective address (EA) to be translated, then uses that address to determine the physical address in memory corresponding to the effective address. During a fetch from memory, the first step in the process is to determine the specific effective address that must be fetched. This determination is usually calculated with some type of adder circuit. The address calculation is followed by a fetch from a local cache if possible, and is completed with the actual delivery of results from the requested location in physical memory.
While the local cache fetch is being executed, a second circuit executes an address translation on the fetch address so that the correspondence between the effective address and the physical address is known. Absent some alternative, a full translation of the effective address to the physical address is required to retrieve the instruction or data from memory. However, the complete translation of an effective address to a physical address is lengthy process. Therefore, faster methods of determining the physical address to be accessed may be executed concurrently with the full address translation process.
A translation cache, also known as a translation array or translation lookaside buffer (TLB), containing known address translations may be employed to speed translation. The entries in the translation lookaside buffer contain translations of effective address to physical address for data in the local cache. When a translation array is employed, the cached addresses are indexed by a field from the effective address. To access the translation cache, an effective address must be generated, followed by a wordline decode to provide a signal indicating which entry in the translation cache should be employed.
The generation of an effective address is accomplished by adding two 32-bit numbers to form the next effective address to be translated and fetched. Conceptually, this effective address is generated by taking the previous fetch address and adding a 32 bit offset to form a 32 bit result address. Efficient implementations of the necessary 32 bit adder are known. However, a 32 bit sum result requires more time to generate that sum results of smaller sizes. It would be desirable therefore, to reduce the process of effective address generation to an addition of smaller numbers. It would also be advantageous to combine the addition process necessary to generate and effective address with the decode process utilized to determine which translation cache entry should be employed. Either improvement would speed performance of the processor's address translation mechanism, significantly improving the overall performance of the processor. It would be desirable for the improvement to comprise a simple, cost effective modification to existing processor designs.